Jordan Anderson and Dr. Doran Wilde, Electrical and Computer Engineering
The goal of this project was to write a hardware description of a new microprocessor in a language called VHDL that can be built inside a field-programmable gate array (FPGA). The processor will run real-time applications and take advantage of the programmability of FPGA hardware by implementing several functions that are typically done in software, such as task resource allocation. The description will be used to create multiple processors that function together in one FPGA.
FPGAs are becoming the best choice for low-volume or short-lifetime products. “Field Programmable” means that the product may be reprogrammed (reconfigured) after being programmed with the initial design. This flexibility greatly reduces the cost of design changes.
Our goal in this project was to exploit this attribute of the FPGA to make a system that will work more efficiently for real-time systems. Real-time systems have different requirements than other systems. Rather than just running a program from start to finish, they have any number of tasks ready to run, waiting for input from outside the system. The system needs to switch between tasks efficiently and also have processing power to execute them as fast as needed.
The microprocessor design we created is designed to be able to manage multiple tasks. It is also designed to work in a multiprocessor setting. This means that different processors can run different tasks, but communicate with each other and share resources and data. Since the processor was described in VHDL, it can be easily adjusted to meet specific needs of different applications.
The creation of a multiprocessor system is a very complicated task. The first step was to decide on the set of instructions that would control the system and facilitate our goal of real-time processing. We had to include all of the instructions that are standard in other processors as well as create a few new ones specific to our needs. They mostly deal with sharing information between processors and managing tasks. Once that was done, the next step was to design a single processor. To facilitate the design of the processor, we took a top-down approach. This involves looking at the processor as a collection of functional units, and designing those units so that they interact with each other, and then filling in the details of each unit. The majority of the units within the processor are very similar to other processors, so there was not a lot of difficulty in designing these units, because they are very standard.
The next step after the initial design of the circuitry was to use simulation tools to test what we had designed. The testing is to verify that each part of the processor performs correctly for any combination of inputs. This is a very time intensive part of the development, because there are a wide variety of input combinations for each part and there because there are many parts, so the time required to test the entire processor is proportional to the complexity and number of parts that make it up. We tested most of the Arithmetic Logic Unit (ALU) which is a large part of the processor. It performs the math and logic functions of the processor. We also tested the processor as a whole, once the parts were all made. Initial tests were simple, but successful. More testing is required before the processor will be useful.
Once the design of one processor was completed and partially tested, the next step was to create the circuitry to connect multiple processors together and make them share the resources that are available to all of the processors. One of the most difficult areas of this project is to share these resources effectively, so that all of the multiple processors are used efficiently. Our plan is to create a resource matrix that will control the availability of the different resources and an arbitrator to control which processor is allowed to access the matrix. If a processor needs a specific resource, say a queue, it must wait until the arbitrator allows it to check the resource matrix, and then the resource matrix will tell the processor whether or not it is allowed to have the resource. This arrangement is useful in real-time applications because each processor can be dedicated to a certain task, yet the resources can be shared and controlled by all of the processors. The resource matrix and arbitrator have been initially designed, but have not undergone testing yet.
Once the multiprocessor system is completely tested, it will allow for further research into the benefits and problems of multiprocessor real-time systems. This research will be aided by the fact that the system can easily be reconfigured to improve performance. In traditional processor design, the testing has to be done in software simulation because of the cost of making hardware. Since we are using FPGAs, we can do the testing in hardware by programming the FPGA. This will aid in getting more accurate results.
This research project was a successful as a venture into processor design and working with the issues that surface with general system design. The creation of this processor will aid in further research that will benefit this area of design.