Alexander Petrie and Dr. Shiuh-hua Wood Chiang, Electrical and Computer Ingineering Department

Introduction

Brain diseases, such as depression and strokes, affect an ever-increasing number of the human population. Much scientific research has been devoted to finding ways towards alleviating the negative symptoms of these diseases. However, much more research must be conducted before these maladies are no longer a problem. Neural implantable devices are an essential part of such research. These tiny, electronic devices monitor electrical brain activity and wirelessly transmit the collected data to computers so scientists can analyze it. A common issue with these neural recording devices is battery life. Current technology allows for a battery to last only 3-5 years. Often, the devices need to be replaced, which requires invasive brain surgery and significant medical cost. Our ongoing research project is to design an ultra-low power Analog-to-Digital Converter (ADC) that can be used in a low power neural recording device to minimize invasive replacement surgeries. Our primary way of achieving this is to design an ADC that uses a 0.2V power supply. The current state-of-the art ADCs use a minimum of a 0.3V power supply. Therefore, our ADC will drastically improve on current designs. However, when such a low supply voltage is used, the ADC speed performance is extremely degraded. We have chosen to design a Successive Approximation Register (SAR) ADC because that design has an inherent low power consumption. In our SAR design, we use various circuit design techniques to improve the speed of the ADC circuitry, especially the comparator.

Methodology

A vital building block of our SAR ADC is the comparator. The comparator is an electronic circuit which asserts a low or high signal, depending on the difference in inputs. In order for our ADC to properly function with a 0.2V supply, it is imperative that the comparator accurately asserts its output as quickly as possible, while adding minimal electrical noise to the system. Additionally, the comparator must consume low power in order to minimize the overall power consumption of the ADC. Over the course of the school year, I have tested four different comparator designs with a power supply of 0.2V, analyzing the trade-offs in power, speed, and noise. The goal of this research was to find an optimal comparator design for use in our SAR ADC. The four different comparator circuits I researched are shown in Figures 1-4. I used Cadence Virtuoso software to simulate the different comparator designs. First, I performed a power and speed analysis of each comparator by measuring the average current drawn by the power supply over several clock cycles. The power was then associated to the speed with which the comparator asserts the output. This analysis was used to determine which comparator was able to perform the fastest given a certain power consumption. I then conducted a noise analysis of the four designs to determine which comparator would inject the least amount of noise into an electrical system. This analysis was done by slowly increasing the input difference from zero until the comparator output was asserted correctly despite circuit noise.

Results

The power analysis results are summarized in Table 1. After performing this analysis, I decided that Comparator design 1 had such a high power consumption that it would be useless for our ADC. I immediately was able to disregard that design and perform a noise analysis on the remaining three designs. The results of the noise analysis can be seen in Figure 2. This figure is a graph of the normal distribution curve of each comparator. They are all fairly similar but the best noise performance can be seen in Design 4 because the curve is the narrowest.

Discussion

These results show that the four comparators have different strengths and weaknesses. Comparator design 1 has very poor speed and noise performance, and would not be helpful to use in our SAR ADC. Comparator design 2 is somewhat slow, and has fairly poor noise performance. It is slow because this design has four transistors between the power supply and ground, thereby consuming more headroom. Comparator design 3 is the fastest of the four due to its simplicity, and has medium power and noise performance due to the sizing of the transistors. Comparator design 4 has a medium speed, and the best power and noise performance because the transistors can be sized relatively small. In choosing the desired comparator, it is important to evaluate what performance metric is the most important, and consider the trade-offs of each design.

Conclusion

In our study of these comparators operating at a 0.2V power supply, we have discovered that there is no perfect solution that gives the best speed, power, and noise performance. I believe that Comparator design 3 is the best choice for our ADC given our results. This will cost us a little in terms of power, but I believe that we can find ways to save power elsewhere in the ADC so our overall power consumption will still be low and we will still achieve our goal of an extremely low power SAR ADC.